Strategy to Disentangle Multiple Faults to Identify Random Defects within Test Structures
نویسندگان
چکیده
Defect inspection is required for process control and to enhance chip yield. Electrical measurements at test structures are commonly used to detect faults. To improve the accuracy to evaluate the defects that have caused such faults, this paper presents a strategy to analyze single and multiple faults to precisely determine the number, layer and location of randomly distributed defects within a test structure layout. For that we first discuss the possibilities to analyze faults within known test structure layouts. Then, we present modified test structure layouts to improve the analysis of multiple faults. Finally we introduce a methodology to disentangle multiple faults by calculating and comparing the probability of possible defect locations within large test structure layout areas.
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